Automatic test pattern generation

ABSTRACT

A method of generating digital test patterns for testing a number of wiring interconnects is described. A first set of test patterns is generated; the number of test patterns in the first set is related to said number of wiring interconnects, and defines a first set of code words. From the first set of code words, a second set of code words is selected. The number of code words in the second set is equal to said number of wiring interconnects, and the selection of the second set of code words is such that the sum of the transition counts for the code words in the second set is minimized.

The present invention relates to automatic test pattern generation, andin particular to test pattern generation that can prevent ground-bounceduring testing of integrated circuits.

In digital systems, there are usually a large number of wiringinterconnects between components. It is an important part of the designand manufacturing process to be able to test these interconnects usingknown test signals. The interconnects will be referred to a “nets” inthis specification.

Many test generation algorithms have been proposed previously. Forexample, see José T de Sousa and Peter Y K Cheung, “Boundary-ScanInterconnect Diagnosis”, Kluwer Academic Publishers, Dordrecht, TheNetherlands, 2001. The objective of test generation algorithms is togenerate the smallest possible set of test patterns, with certainminimum detection and diagnostic properties. Fault models that aretypically addressed by such test generation algorithms are single-netshorts and multiple-net bridges.

In order to test a number of interconnect wires (nets) between two ormore digital components, combinations of digital test stimuli areapplied to net inputs, the responses are observed at net outputs, andcompared to expected responses. It is assumed that there is full controlover the inputs of the nets, and that the outputs of the nets are fullyobservable.

In the following description, the following terms for the test stimuliare used. These terms are illustrated in FIG. 1 of the accompanyingdrawings.

-   -   Test Pattern: A test pattern 2 is a set of test data bits that        are applied simultaneously, in parallel, to the nets under test.        In FIG. 1, the test patterns are shown as the columns of the        test data. Test patterns are sometimes known as Parallel Test        Vectors (PTVs).    -   Code Word: A code word 4 is the list of test data bits applied        serially to an individual net during the test In FIG. 1, code        words are the rows in the test data. Code words are sometimes        known as Sequential Test Vectors (STVs).

Jarwala and Jau (Najimi Jarwala and Chi W Jau, “A New Framework forAnalyzing Test Generation and Diagnosis Algorithm for WiringInterconnects”, Proceedings IEEE International Test Conference (ITC),pages 63-70, October 1989) described the following deterministic faultmodel for wiring interconnects:

-   -   Multi-net faults are bridging faults that create shorts between        two or more nets, and which have the following characteristics:    -   Wired-OR: In case of dominant ‘1 ’ drivers, the short behaves        like a logical ‘wired OR’ between the shorted nets.    -   Wired-AND: In case of dominant ‘0’ drivers, the short behaves        like a logical ‘wired AND’ between the shorted nets.    -   Strong-Driver: A specific driver dominates the shorts, and hence        the shorted nets follow the dominant driver.    -   Single-net faults include “stuck-at” faults and “stuck-open”        faults on a single net, have the following characteristics:    -   Stuck-at-0: The fault is such that the data value on the net is        always read as logical ‘0’.    -   Stuck-at-1: The fault is such that the data value on the net is        always read as logical ‘1’.

The requirement for testing shorts is that every net must get a uniquecode word. If the nets are fault-free, each response is unique. In caseof a short, the nets involved in that short have the same response.Therefore, these responses are no longer unique and the short isdetected. William Kautz (William H Kautz. Testing of Faults in WiringInterconnects. IEEE Transactions on Computers, Vol C-23 (No 4): 358-363,April 1974) proposed a test for shorts which has become known as theCounting Sequence Algorithm. A simple binary counting algorithmgenerates the code words. For k nets, log₂k test patterns are required.The Counting Sequence Algorithm guarantees the detection of all shortswith the minimum number of test patterns.

In order to guarantee that every net is tested for stuck-at-0 opens,every code word needs to contain at least one ‘1’. Likewise, forstuck-at-1 faults, every code word needs to contain at least one ‘0’.The Counting Sequence Algorithm does not guarantee this. Therefore, Goeland McMahon (P Goel and M T McMahon, “Electronic Chip-In-Place Test”.Proceedings IEEE International Test Conference (ITC), pages 83-90,October 1982) proposed a test generation algorithm that has become knownas the Modified Counting Sequence Algorithm. The main idea is that openfaults can be detected if we forbid the all-zeros and all-ones codewords. Hence, for k nets, log₂(k+2) test patterns are needed, which canbe generated again by a simple binary counting algorithm, which startsat one, instead of at zero. The Modified Counting Sequence Algorithmguarantees the detection of all shorts and opens with the minimum numberof test patterns.

Another interconnect text generation algorithm, published by Eerensteinand Muris (Lars Eerenstein and Math Muris, “Method for Generating TestPatterns to Detect an Electric Short circuit, a Method for TestingElectric Circuitry While Using Test Patterns So Generated, and a TesterDevice for Testing Electric Circuitry with such Test Patterns”, U.S.Pat. No. 5,636,229), is known as the LaMa Algorithm. The LaMa algorithmis based on the Modified Counting Sequence Algorithm, but increments bythree rather than by one. The LaMa algorithm requires log₂(3k+2) testpatterns for k nets.

The above-mentioned test generation algorithms guarantee detection offaults. However, next to detection of faults, diagnostic resolution isoften another important property of a test. Jarwala and Jau describedthe situation of aliasing, which obscures the diagnostic resolution.Aliasing occurs if the faulty response of a faulty net is equal to thefault-free response of another, fault-free net. In this case, we cannotdetermine whether the fault-free net also suffers from the fault at thefault net Paul T. Wagner, (“Interconnect Testing with Boundary Scan”,Proceedings IEEE International Test Conference (ITC), pages 52-57,October 1987) presented the True/Complement Test Algorithm, whichenhances the (Modified) Counting Sequence Algorithm in order to preventaliasing. Wagner's method applies all test patterns of the originalCounting Sequence Algorithm, followed by the same test patterns withinverted values. Due to the inverted test patterns, all-zeros andall-ones code words will not be generated. Therefore, it is notnecessary to exclude the numbers 0 and k−1 in the counting sequence.Hence, the True/Complement Test Algorithm requires 2 log₂k testpatterns. The True/Complement Test Algorithm guarantees that every codeword contains an equal number of zeros and ones, due to the inversion.

In case of a ‘Wired-OR’ fault with another net, in the response word thenumber of ones is increased and the number of zeros is decreased.Likewise, in case of a ‘Wired-OR’ fault with another net, in theresponse word the number of ones is increased the number of zeros isdecreased. Likewise, in case of a ‘Wired-AND’ fault with another net,the number of zeros is increased and the number of ones is decreased. Incase of a stuck-at open fault, all response values will be eitherall-zeros or all-ones. Hence, in every fault case the numbers of zerosand ones changes, such that the response word does not contain an equalnumber of zeros and ones any more. Therefore, a faulty response willnever be equal to a fault-free response of another net, and hence, theTrue/Complement Test Algorithm is aliasing-free. In the example of FIG.2(d), with k=4, we need 2. ┌²log⁴┐=4 test patterns. The code words are1100, 1001, 0110 and 0011, and they can be arbitrarily assigned to thefour nets. FIG. 1 illustrates True/Complement Test Algorithm testpatterns for the five nets (net 1 . . . net 5) shown.

Recently, preventing ground bounce has become a new constraint for testgeneration algorithms. Ground bounce refers to the phenomenon ofshifting ground and power voltage levels, for example between theIC-internal ground and power levels and those at the board, and can becaused by a large number of values switching simultaneously on an IC.Ground bounce can be prevented by introducing an upper limit on theamount of switching activity between consecutive test pattern testpatterns. This limit is known as the Simultaneous Switching Output Limit(SSOL).

During the regular operation of an IC, there is much internal switchingactivity amongst transistors. Too much activity can cause surges incurrent demand from the power-supply and cause the IC-internal power orground levels to fluctuate considerably. This in turn, can causespurious pulses to be generated on critical signals, such as systemclocks or master resets, thereby causing spurious behavior in the IC.For example, see Hans Peter Richter and Norbert Münch, “Boundary-ScanTest Triumphs Over Ground-Bounce”, Test & Measurement World Europe,August/September 1997, or Amitava Majumdar, Michio Komoda, and TimAyres, “Ground Bounce Considerations in DC Parametric Test Generationusing Boundary Scan”, Proceedings IEEE VLSI Test Symposium (VTS), pages86-91, April 1998.

Ground bounce can have a negative impact on the operation of the IC. Ifthe IC-internal ground voltage level rises to the threshold voltage ofthe IC-internal logic, there exists the likelihood of invalid logicbehavior. In the case of Boundary-Scan-equipped ICs, ground bounce canresult in spurious test clocks (TCKs), which, in turn, can causeon-board Boundary-Scan devices to go out of synchronization.

Ground bounce can be prevented by designing ICs (or boards) such thatthey can handle large amounts of switching activity within the IC (orbetween ICs on the board). The switching activity during test istypically higher than during normal (non-test) operation. By its verynature, testing sets up sensitive paths through a circuit therebycausing many outputs to change value. In order to save test time, it isoften an objective of test generation algorithms to obtain the highestpossible fault coverage with a minimum number of test patterns. Thisincreases still further the amount of internal switching activity pertest pattern. ICs and boards are designed to handle ground bounce duringnormal operation and during test operation. In fact, the IEEE 1149.12Boundary-Scan Standard mandates that there should be no ground-bounceinside the device during all test operations based on the use of theboundary-scan register. The problem is that at board level, with allon-board boundary-scan devices in EXTEST test mode for interconnecttesting, there is no guarantee that board-level ground bounce will notoccur, even though each device is within its ground bouncespecification. In fact, there is a high probability that ground bouncewill occur if there are more than a few thousand Boundary-Scan toBoundary-Scan interconnects.

Richter and Münch reported on ground bounce problems during EXTESTtesting between 1149.1-compliant ASICs on an industrialtelecommunications board. All the ASICs met their electrical groundbounce specification and simulation confirmed correct operation of theASICs under normal operation with at most 50% of the ASIC outputsswitching simultaneously. The ASIC designers did not consider thepossibility that many (or even all) boundary-scan outputs might switchsimultaneously (worst-case EXTEST), even though that was what happenedduring board testing.

Ground bounce can be prevented at board level by controlling the degreeof switching activity in the test patterns generated and applied acrossthe interconnects. This can be done by introducing an upper limit on howmany Boundary-Scan outputs can be simultaneously switched in thetransition from one test pattern to the next. In this description, thisupper limit is referred to as the Simultaneously-Switching Outputs Limit(SSOL). In general, the SSOL should be derived and defined by the boarddesigner responsible for the electrical design of the board. Manyvendors of board-level interconnect ATPG tools have added SSOLconstraints into their products.

The SSOL constraint restricts the maximum number of data bit transitionsbetween two consecutive test patterns. The number of bit transitionsbetween consecutive test patterns is known as the Hamming distance, andis illustrated in FIG. 2. In FIG. 2(a) six test patterns (p₁ to p₆) areshown and the Hamming distances 6 between consecutive test patterns arealso shown. It can be seen that two of the consecutive pairs of testpatterns have Hamming distances greater than assumed level of SSOL of 2.

It is therefore necessary to modify the test patterns in order to removethese violations. A previously considered method for removing theviolations is to insert additional test patterns between the violatingpairs of test patterns. In the present case, as shown in FIG. 2(b), twoadditional test patterns p_(2i) and p_(5i) are added to remove theseviolations. AR of the pairs of test patterns in FIG. 2(b) have Hammingdistances less than the SSOL level.

However, incorporating an SSOL constraint into test generation generallyleads to an increase in the number of test patterns, and hence testtime, because of the need to insert additional test patterns.

It has been shown in Erik Jan Marinissen, Bart Vermeulen, Henk Hollmann,and Ben Bennetts, Minimizing Pattern Count for Interconnect Tests UnderA Ground-Bounce Constraint. IEEE Design & Test of Computers, 20(2),March/April 2003 that the conventional approach of simply insertingadditional test patterns to overcome SSOL violations can lead to anunnecessarily large test set. There are two degrees of freedom that canbe exploited in order to reduce the number of additional test patternsthat need to be inserted, while maintaining all detection and diagnosticproperties of the original test set.

The Marinissen et al paper will now be described in more detail in orderto describe fully the background to the present invention.

The method will be described with reference to the True/Complement TestPattern generation algorithm described above, but it will be readilyappreciated that the method is able to operate on test patternsgenerated by any algorithm or approach.

The method uses two basic steps: code word subset selection, and testpattern re-ordering (and insertion). The overall method is illustratedin FIG. 3. At step 10, an automatic test pattern generation algorithm isused to generate a complete set of test patterns.

At step 12(120, 121, 122) code word subset selection is performed usingany method (120), a transition count method (121), or a difference countmethod (122). The results of the selection are fed to a re-ordering step14, which reorders the test patterns using any method (141), or a greedymethod (142) to minimize the number of SSOL violations in the testpattern set. The various methods will be described in more detail below.

Following reordering, additional test patterns can be inserted wherenecessary (step 15) in order to remove any remaining SSOL violations.

The selection of a code word subset will now be described in more detailFor k nets, a test generation algorithm requires p(k) test patterns.With p(k) test patterns, the algorithm generates c(k) unique code words,such that k≦c(k). The functions p(k) and c(k) depend on the testgeneration algorithm. For example, for the True/Complement TestAlgorithm p(k) and c(k) are given by the following:┌p(k)=2 log₂ k┐┌c(k)=2^(p(k)/2)=2^(log) ₂ ^(k)┐In many practical cases, the algorithm generates more code words thanstrictly necessary, i.e., k<c(k), because k, p(k), and ck) are allintegers. This means that the expressions have ceil operators that roundoff any non-integer values to the nearest higher integer values. Theseceil operators cause that in many cases k<c(k).

Accordingly, it is possible to choose a subset of the total number c(k)of generated code words to be applied during the test. Such subsetselection will not affect the detection and diagnostic properties of atest; or test time.

There are $\begin{pmatrix}{c(k)} \\k\end{pmatrix} = \frac{{c(k)}!}{{k!} \cdot {\left( {{c(k)} - k} \right)!}}$possible subsets available from which to choose. As an example, considerthe True/Complement Test Algorithm for k=257. According to the above,c(257)=2^(log) ₂ ²⁵⁷=2⁹=512. Therefore, there are $\begin{pmatrix}512 \\257\end{pmatrix} \approx {4.7 \times 10^{152}}$alternative code word subsets.

The subset selection procedure searches for the subset of code wordsthat leads to the smallest test pattern set without SSOL violations.

The code word subset selection can be performed by one of two heuristictechniques, which will be described below.

The first possible heuristic technique is based upon a transition count,and is illustrated in FIG. 4. The example of FIG. 4 represents the casefor k=5, which yields 6 test patterns and eight code words. In FIG. 4(a)a complete set (c₁ to c₈) of test patterns is shown, together with thecount 30 of the number of bit transitions therein. Using the transitioncount heuristic method, the k(=5) code words that are required areselected as the 5 code words having the lowest transitions counts. Whereonly a selection of code words having the same transition count isrequired, the selection is made arbitrarily.

FIG. 4(b) illustrates the selected code words (c₁ c₂ c₄ c₅ c₈), togetherwith the Hamming distances 30 between consecutive test patterns. In thiscase, it can be seen that the subset form a test pattern set that has noviolations for SSOL=2, and so no further processing would be required.Naturally, and especially for large values of k, reordering and possibleinsertion could be required.

The second heuristic approach uses a difference count method, and thisis illustrated in FIG. 5. FIG. 5(a) shows a complete test pattern set(c₁ to c₁₆), for the situation when k=9, and SSOL=3, generated using theTrue/Complement method. Each code word has an associated differencecount, which is equal to the number of differences between the bits inthe first half of the code word and those in the second half of the codeword.

The code words having the lowest difference counts are then selected toprovide the correct number k of code words. When a selection betweencode words having the same difference count is to be made, thisselection is made on an arbitrary basis.

FIG. 5(b) shows the selected subset of code words, together with theHamming distances between consecutive pairs of test patterns. It can beseen that test patterns several of the test pattern pairs fail theSSOL<=3 test, and so further processing will be required. The results ofthe further processing (reordering), to be described in detail below,are shown in FIG. 5(c).

Reordering and insertion of the test patterns will now be described inmore detail.

Reordering of the test patterns is carried out on the subset of codewords selected during the previous stage. Accordingly, there are p testpatterns and k code words.

Initially, a so-called SSOL Violations Graph is constructed. Such agraph is shown in FIG. 5 and comprises a weighted, fully connected, andundirected graph. The nodes of the graph correspond to the p(k) testpatterns. The edge between each pair of nodes is given a weightdependent upon the hamming distance between the nodes in the pair. Theweight of an edge represents the number of SSOL violations between thosetwo nodes.

The problem of finding the route through the nodes of the graph can beseen to be a version of the traveling salesman problem (TSP). In termsof the SSOL Violations Graph, it is necessary to find a route throughall nodes of the graph, such that the summed weight of the edgesencountered along the tour is minimized.

This problem is equal to the optimization variant of the well-knownTraveling Salesman Problem, M. R. Garey and D. S. Johnson, Computers andIntractability—A guide to the theory of NP-Completeness, W.H. Freemanand Company, San Francisco, Calif., USA, 1979.

The Traveling Salesman Problem (TSP) is briefly described, and can besummarized as follows. Given a set C of m cities, with distancesd(c_(i),c_(j)) for each pair of cities c_(i),c_(j)εC, and a positiveinteger B. Is there a tour of C having length B of less?

In practical terms, the time needed to compute an optimal solutionincrease exponentially with the problem instance size. The probleminstance size is determined by the number of nodes (test patterns).Fortunately, the problem instance size for board-level interconnecttesting is not very large. The number of test patterns is of the orderof log₂k, and hence, even for boards with thousands of nets, there arebetween 10 to 20 test patterns. Therefore, it seems feasible for mostpractical problem instances to solve this problem exhaustively, i.e., byenumerating all possible tours in the graph. Alternatively, there areeffective and efficient heuristic algorithms for TSP available in theliterature, that are able to solve this problem with close-to-optimalsolutions in short compute tines. For example, see David .S Johnson andLyle A. McGeoch, “The traveling salesman problem: A case study”, inEmile H. L Aarts and Jan-Karel Lenstra, editors, “Local Search inCombinatorial Optimization”, pages 215-310, John Wiley & Sons Ltd.,Chichester, England 1997.

FIG. 5(b) illustrates a SSOL violations graph for k=5, and s=2, withFIG. 5(a) showing the unordered test pattern set that makes up the nodesof the graph. It can be seen that the unordered test pattern set has twoinstances of pairs of test patterns which violate the SSOL criterion.

In FIG. 5 (b) bold arrows indicate the SSOL-violation-free tour throughthe graph. FIG. 5(c) shows the corresponding resultant test set, inwhich the test patterns are ordered according to the minimizedSSOL-violation tour in the graph.

After running a TSP Solver, there are two possible outcomes: (1) a tourwith summed weight zero is obtained, or (2) a tour with summed weightlarger than zero is obtained. In the first case, an ordering of the testpatterns that meets the SSOL constraint has been found. In the lattercase, an ordering of the test patterns has been found that still has oneor more SSOL violations. This might be due to the fact that there is nottour with summed weight zero, or there is such a tour, but the heuristicTSP solver used was not capable of finding it. In any case, it isexpected that the number of SSOL violations is relatively low, asminimizing the summed weight of the tour was the objective function ofthe TSP Solver.

Remaining SSOL violations case be resolved by inserting one or moreadditional test patterns in between two consecutive test patterns thathave an SSOL violation. If consecutive test patterns p₁ and p₂ havew(p₁, p₂) SSOL violations (with w(p₁, p₂)>0), then it is necessary toinsert w(p₁,p₂)/s additional test patterns in order to resolve all SSOLviolations between those two patterns.

In FIG. 5(c), it can be seen that one pair of test patterns violate theSSOL criterion, and so an additional test pattern must be insertedbetween those two test patterns to remove this violation.

The Marinissen et al. paper provides equations for theoretical upper andlower bounds for the minimal number of test patterns for k nets underthe SSOL constraint s.

It is therefore desirable to provide a test pattern generation algorithmthat can incorporate a SSOL constraint, but that also further minimizesthe number of test patterns to be generated, and makes use of additionaloptimization.

Embodiments of the present invention therefore seeks to provide such analgorithm, to provide a method that allows incorporation ofSSOL-violation-free consecutive test patterns into any given testgeneration algorithm.

According to one aspect of the present invention, there is provided amethod of generating digital test sets for testing a number of wiringinterconnects, each test set comprising a matrix of bits, which matrixdefines a first plurality of test patterns and a second plurality ofcode words, wherein the bits of each test pattern are for application torespective wiring interconnects in parallel with one another, and thebits of successive test patterns for application to an interconnect forma code word for that interconnect, and wherein each code word has atransition count related to a number of bit value transitions therein,the test set having a total transition count related to the sum of thetransition counts of the code words in the test set, the methodcomprising the step of generating a test set which has a totaltransition count which is less than a predetermined threshold value, thepredetermined threshold value having a predetermined relationship withthe number of test patterns in the test set.

FIG. 1 illustrates test patterns and code words;

FIG. 2 illustrates test stimuli for five nets for the True/ComplementTest Pattern Generation Algorithm;

FIG. 3 illustrates a method embodying one aspect of the presentinvention;

FIG. 4 illustrates a first method of code word subset selection;

FIG. 5 illustrates a second method of code word subset selection;

FIG. 6 illustrates a method for reordering test patterns;

FIG. 7 illustrates a test matrix and a transition matrix;

FIG. 8 illustrates selection of code words;

FIG. 9 illustrates a method embodying the present invention;

FIG. 10 illustrates another method embodying the present invention;

FIG. 11 illustrates code word length selection;

FIG. 12 illustrates test pattern counts; and

FIG. 13 illustrates test pattern count reduction.

A preferred embodiment of the present invention will now be describedwith reference to the accompanying drawings.

Firstly, a relationship is analyzed between the binary contents of aninitial test pattern set and the number of test patterns that need to beinserted to resolve any violations of the maximum Hamming distanceconstraint for consecutive test patterns.

FIG. 3(a) illustrates a test pattern matrix C, where the rows correspondto the k code words and the columns to the b test patterns. The k codewords are denoted by C₁, . . . C_(k). C_(i,j) refers to bit j in codeword C_(i), for 1≦i≦k and 1≦j≦b. The test patterns are denoted by p₁ . .. p_(b), where p_(j)=(C_(1,j), . . . ,C_(k,j)) is the jth column of thetest pattern matrix C.

As transitions and transition-counts are important in the analysis, analternative notation of test pattern matrix C is used. A transitionmatrix T is calculated, which comprises a k×(b−1) matrix T and k initialcode word values C_(i,1). A transition matrix T is illustrated in FIG.3(b). The relationship between the matrices C and T is given by:$T_{i,j} = \left\{ \begin{matrix}{1,} & {{{if}\quad C_{i,j}} \neq C_{i,{{j + 1};}}} \\{0,} & {otherwise}\end{matrix} \right.$For j=1 . . . b−1, the Hamming distance between consecutive testpatterns pj and Pj+1 is defined as:d _(j) =d _(H)(p _(j) ,p _(j+1))For simplicity, it is assumed that consecutive test patterns aredistinct,that is, that d_(j)>0 for all j.Given this assumption, if test pattern matrix C is used in combinationwith an SSOL constraint s, then [d_(j)/s]−1 test patterns have to beinserted between p_(j) and p_(j+1). Hence, after insertion the totalnumber of test patterns P_(s) required under SSOL constraint s based onthe given test set satisfies the following:$P_{s} = {{b + {\sum\limits_{j = 1}^{b - 1}\quad\left( {\left\lceil \frac{d_{j}}{s} \right\rceil - 1} \right)}} = {1 + {\sum\limits_{j = 1}^{b - 1}\quad{\left\lceil \frac{d_{j}}{s} \right\rceil.}}}}$Let τ_(i), for i=1 . . . k, denote the number of transitions in codewordc _(i), i.e., τ_(i) =#{jε{1, . . . ,b−1}|C _(i,j) ≠C _(i,j+1)}.The aim is to derive lower and upper bounds for the total number of testpatterns P_(s), in terms of the total number of transitionsτ_(tot)=Σ_(i=1) ^(k)τ_(i) in the test pattern matrix C. The analysis isbased on the definition of the total distance d_(tot) of the test by:$d_{tot} = {\sum\limits_{j = 1}^{b - 1}\quad d_{j}}$

The total number of transitions in a row of test pattern matrix C isgiven by number of ones in the corresponding row of transition matrix T.The Hamming distance between consecutive test patterns is given by thenumber of ones in the relevant column of transition matrix T.Accordingly, both τ_(tot) and d_(tot) count the total number of ones inthe transition matrix T; one does so by rows and the other by columns.

Formally, $\begin{matrix}{\tau_{tot} = {\sum\limits_{i = 1}^{k}\quad\tau_{i}}} \\{= {\sum\limits_{i = 1}^{k}\quad{\sum\limits_{j = 1}^{b - 1}\quad T_{i,j}}}} \\{= {\sum\limits_{j = 1}^{b - 1}\quad{\sum\limits_{i = 1}^{k}\quad T_{i,j}}}} \\{= {\sum\limits_{j = 1}^{b - 1}\quad{d_{H}\left( {p_{j},{p_{j} + 1}} \right)}}} \\{= {\sum\limits_{j = 1}^{b - 1}\quad d_{j}}} \\{= d_{tot}}\end{matrix}$

The fact that total Hamming distance is equal to the total number oftransition can be used to derive upper and lower bounds for P_(s) thatdepend only on τ_(tot).

A test pattern set consisting of code words of length b contains a totalof τ_(tot) transitions. The total number P_(s) of test patterns, afterinsertions, to satisfy an SSOL constraint s is then given by:${1 + \left\lceil \frac{\tau_{tot}}{s} \right\rceil} \leq P_{s} \leq {\left\lfloor \frac{\tau_{tot}}{s} \right\rfloor + {b.}}$The proof of this expression is given below.Let τ_(tot) =qs−r, with 0≦r<s. For each j, let d_(j)=q_(j) s−r _(j) with0≦r_(j)<s.According to expression given above,$\tau_{tot} = {d_{tot} = {{\sum\limits_{j = 1}^{b - 1}\quad d_{j}} = {{s{\sum\limits_{j = 1}^{b - 1}\quad q_{j}}} - {\sum\limits_{j = 1}^{b - 1}\quad{r_{j}.}}}}}$From this follows${\sum\limits_{j = 1}^{b - 1}\quad{q\quad j}} = \frac{\tau_{tot} + {\sum\limits_{j = 1}^{b - 1}r_{j}}}{s}$and since |d_(j)/s|=q_(j),$P_{s} = {{1 + {\sum\limits_{j = 1}^{b - 1}\left\lceil \frac{d_{j}}{s} \right\rceil}} = {{1 + {\sum\limits_{j = 1}^{b - 1}\quad q_{j}}} = {1 + {\frac{\tau_{tot} + {\sum\limits_{j = 1}^{b - 1}r_{j}}}{s}.}}}}$As a consequence$P_{s} = {{1 + \frac{\tau_{tot} + {\sum\limits_{j = 1}^{b - 1}r_{j}}}{s}} \geq {1 + \frac{\tau_{tot}}{s}}}$and$P_{s} = {{1 + \frac{\tau_{tot} + {\sum\limits_{j = 1}^{b - 1}r_{j}}}{s}} \geq {1 + \frac{\tau_{tot} + {\left( {b - 1} \right)s}}{s}} \leq {\frac{\tau_{tot}}{s} + {b.}}}$Since P_(s) is an integer, the theorem follows.

From this theorem, it is concluded that for fixed code word length b,the total number of test patterns after insertion under an SSOLconstraint s can be small only by using a collection of code words forwhich the total number of transitions is small.

Accordingly an embodiment of the present invention seeks to minimize thetotal number of transitions in the test pattern matrix C.

A further aspect of the present invention will now be described. Thisaspect results in a method that enables the choice of an almost optimalset of k code words of any fixed length b, which minimizes the totalnumber of test patterns required under an SSOL constraint s. In order tohave at least k code words available, 2^(b)≧k. So, it is assumed thatb≧b_(min)=|log₂ k|.

This aspect of the present invention uses the following code wordselection method. Choose all words with 0 transitions, then all wordswith 1 transition, up to all words with t−1 transitions, and finallysome additional words with t transitions. Here t is such that the numberk of required code words is larger than the number of words of length bwith at most t−1 transitions, but not larger than the number of words oflength b with at most t transitions.

This technique is illustrated in FIG. 8, where the test pattern matrix Cand the transition matrix T are shown. The rows of the two matrices areordered from zero transitions (matrix C) or zero ones (matrix T) at thetop to t transitions or ones at the bottom of the Fig. In accordancewith this embodiment of the invention the code words are selected fromthe top of the matrices, downwards until the required number of k codewords have been selected. For both test set representations, the fig.shows by means of gray shading which code words are generated.

It is useful to note that that total number of transitions in a testpattern set chosen in this way does not depend on the choice ofparticular code words with t transitions, and is by construction theminimal number of transitions in any set of k code words of length b.This is denoted by τ_(tot)(b). In order to analyze algorithms based onthis method and to be able to compute τ_(tot)(b), the following resultis required:

The number of words of length b−1 with precisely i ones is equal to$\begin{pmatrix}{b - 1} \\i\end{pmatrix}.$From the correspondence between the k×b code word matrix C and thek×(b−1) transition matrix T as indicated in FIG. 7, it can be seen thateach of these words corresponds to precisely two code words with itransitions.

Let k_(i) be the number of code words with i transitions that areincluded in the test set. In order to minimize the total number oftransitions τ_(i)ik_(i) in the test set, the code word selection methodchooses as code words all words containing at most t−1 transitions, andsome of the words containing t transitions. So $k_{i} = \begin{pmatrix}{b - 1} \\i\end{pmatrix}$for 0≦i≦t−1 and t is such that${k = {{\sum\limits_{i = 0}^{t}\quad k_{i}} = {{\sum\limits_{i = 0}^{t - 1}{2\begin{pmatrix}{b - 1} \\i\end{pmatrix}}} + k_{t}}}},\quad{{{with}\quad 0} < k_{t}^{\prime} \leq {2\begin{pmatrix}{b - 1} \\t\end{pmatrix}}}$For τ_(tot)(b) we now obtain the expression${\tau_{tot}(b)} = {{\sum\limits_{i = 0}^{t}\quad{ik}_{i}} = {{\sum\limits_{i = 0}^{t - 1}{{i \cdot 2}\begin{pmatrix}{b - 1} \\i\end{pmatrix}}} + {t \cdot k_{t}}}}$This code word selection method is used to derive bounds on the minimalnumber of test patterns p(k, s, b) required in a test set for k nets,using code words of length b, and satisfying an SSOL constraint s. Sinceit was shown above that there exists a test set (in fact, many testsets) using code words of length b for which τ_(tot)=τ_(tot)(b) andsince obviously no such test can have a similar value of τ_(tot), it canbe concluded that:${1 + \left\lceil \frac{\tau_{tot}(b)}{s} \right\rceil} \leq {p\left( {k,s,b} \right)} \leq {b + \left\lfloor \frac{\tau_{tot}(b)}{s} \right\rfloor}$Note that any algorithm using this code word selection method and somespecific method to choose the k_(t) additional code words achieves atotal number of test patterns after insertion that lies within thebounds of this equation.

In particular, this holds for the Transition-Count code word subsetselection heuristic algorithm in Marinissen et al.

In embodiments of the present invention, the upper bound this equationis improved by using an algorithm that has an improved worst-casebehavior. The algorithm makes use of the following relationship:${\max\left( {b,{1\left\lceil \frac{\tau_{tot}(b)}{s} \right\rceil}} \right)} \leq {p\left( {k,s,b} \right)} \leq {1 + {\left( {b - 1} \right)\left\lceil \frac{\tau_{tot}(b)}{\left( {b - 1} \right)s} \right\rceil}}$where k and b are fixed.

There will now be described an algorithm based on the code wordselection method which produces at most$1 + {\left( {b - 1} \right)\left\lceil \frac{\tau_{tot}(b)}{\left( {b - 1} \right)s} \right\rceil}$test patterns satisfying SSOL s, thus establishing the upper bound.

The idea behind this algorithm is the following. The resulting distancesd_(j) after choosing the k_(t) additional code words determine theresulting number of test patterns after insertion. Due to the code wordselection method, the total distance d_(tot)=Σ_(j=1) ^(b−1)d_(j) willalways be the same (namely τ_(tot)(b)), but the precise value of thedistances d_(j) depend on the choice of the additional k_(t) code words.It is desirable to avoid the situation where all d_(j) are slightlyabove a multiple of s, which is the worst-case behavior on which theupper bound is based.

Preferably, all d_(j) should equal to or slightly below a multiple of s,but this seems difficult to guarantee in general. The worst-casebehavior is avoided by ensuring that the distances d_(j) are all aboutequal. In what follows, it is first shown that the part of the distancesd_(j) on code words with at most t−1 transitions is in fact constant,independent of j. Then, it is explained how to choose the remainingk_(t) code words such that the d_(j) remain about equal.

Given d_(j)=Σ_(t=0) ^(t)d_(j,e), where d_(j,e) is the part of theHamming distance between d_(j) and d_(j+1) on code words containing ltransitions, that isd _(j,e) =#{iε{1, . . . ,k}|C _(i,j) ≠C _(i,j+1) and τ_(i) =l}There are only two code words with 0 transitions, i.e. the all-zero andthe all-one code word, and hence d_(j,0)=0. The number of words in T oflength b−1 with l ones that contain a 1 in a given position jε{1, . . .,b−1} is $\begin{pmatrix}{b - 2} \\{\ell - 1}\end{pmatrix}.$Since each such word T corresponds to two code words in C (one beginningwith a 0, the other with a 1) with l transitions that each contributeone to d_(j,e), the result follows.As a consequence,$d_{j} = {{\sum\limits_{\ell = 0}^{t}\quad d_{j,e}} = {{\sum\limits_{\ell = 0}^{t - 1}\quad{2\begin{pmatrix}{b - 2} \\{\ell - 1}\end{pmatrix}}} + d_{j,t}}}$The choice of k_(t) code words containing t transitions will now bedescribed. In the case ${k_{t} \geq \begin{pmatrix}{b - 1} \\t\end{pmatrix}},$all words with t transitions and starting with a zero are chosen inaddition. It is important to note that the part of the distances d_(j)due to code words chosen up to now is constant, independent of j. Now,let k_(t)* be defined by $k_{t}^{*} = \left\{ \begin{matrix}{k_{t},} & {{{{if}\quad 0} \leq k_{t} < \begin{pmatrix}{b - 1} \\t\end{pmatrix}};} \\{{k_{t} - \begin{pmatrix}{b - 1} \\t\end{pmatrix}},} & {{otherwise}.}\end{matrix} \right.$For later use, it is to be noted that$0 \leq k_{t}^{*} \leq {\begin{pmatrix}{b - 1} \\t\end{pmatrix}.}$Then, it is still necessary to choose k_(t)* additional code words ttransitions (all starting with 0 if $k_{t} \leq \begin{pmatrix}{b - 2} \\t\end{pmatrix}$and with 1 if $\left. {k_{t} \geq \begin{pmatrix}{b - 1} \\t\end{pmatrix}} \right),$or, equivalently, k_(t)* words of length b−1 containing t ones(representing the transitions in the code words). For convenience, wordsof length b−1 containing t ones with subsets of {1, . . . ,b−1} of sizet are identified. Then, in terms of sets, it is still necessary tochoose k_(t)* distinct subsets of size t from {1, . . . ,b−1}. Note thatthe (variable) part of the distance d_(j) on positions corresponding tothese k_(t)* words becomes, in the terms of sets, the frequency f_(j) ofthe occurrence of the element j in these k_(t)* sets. The followingdefinition is therefore needed. A vector f=(f₁, . . . ,f_(n)) is calledbalanced if there is an integer e such that f_(i)ε{e, e+1} for all i=1,. . . ,n.

It is now ensured that the remaining k_(t)* code words are chosen insuch a way that the part of the distances d_(j) on these k_(t)* codewords is balanced. That is, in terms of sets, it is ensured that thefrequencies f_(j) are balanced. The algorithm is based on the followingresult.

Let 1≦t≦n. Suppose there is a balanced integer vector f=(f₁, . . .,f_(n)) with weight f₁+ . . . +f_(n)=mt such that$0 \leq m \leq {\begin{pmatrix}m \\t\end{pmatrix}.}$Then there is a collection S={S₁, . . . ,S_(m)} of m distinct subsets ofsize t of {1, . . . ,n} such that each i occurs in f_(i) of the setsS_(j).

The algorithm embodying this aspect of the present invention performsthe following functions, and is illustrated in FIG. 9. First, at step100, choose numbers t and k_(t) according to:${k = {{\sum\limits_{i = 0}^{t}k_{i}} = {{\sum\limits_{i = 0}^{t - 1}{2\begin{pmatrix}{b - 1} \\i\end{pmatrix}}} + k_{t}}}},{{{with}\quad 0} < k_{t} \leq {2{\begin{pmatrix}{b - 1} \\t\end{pmatrix}.}}}$Next, at step 102, determine the number m=k_(t)* from:$k_{t}^{*} = \left\{ \begin{matrix}{k_{t},} & {{{{if}\quad 0} \leq k_{t} < \begin{pmatrix}{b - 1} \\t\end{pmatrix}};} \\{{k_{t} - \begin{pmatrix}{b - 1} \\t\end{pmatrix}},} & {{otherwise}.}\end{matrix} \right.$Next, at step 104, a selection of code words of length b with at mostt−1 transitions is made, and if m<k_(t) also all words of length b witht transitions and beginning with a 1.

Finally, at step 106, another m words of length b with t transitions andbeginning with a 0 (if m<k_(t)) or a 1 (if m≧k_(t). Here, ifmt=q(b−1)+r, f_(i)=q+1 is chosen for r indices i and f_(i)=q for theremaining b−1−r indices i. This algorithm then ensures that thedistances d_(j) will be balanced. This method can be referred to as“ATPG for Fixed Code Word Length”.

Now, the average Hamming distance is equal to τ_(tot)(b)/(b−1); henced_(j)≦|τ_(tot)(b)/(b−1)| and therefore$\left\lceil \frac{d_{j}}{s} \right\rceil \leq \left\lceil \frac{\tau_{tot}(b)}{\left( {b - 1} \right)s} \right\rceil$It is therefore possible to conclude that this algorithm produces a testset such that, after insertions to satisfy an SSOL constraint s, thetotal number of patterns is (at most)${{1 + \left( {b - 1} \right)} \leq \frac{\tau_{tot}(b)}{\left( {b - 1} \right)s}},$thus proving the upper bound.

Above it was remarked that in order to have at least k code wordsavailable, the code word length b has to be chosen such thatb≧b_(min):=|log₂k|. However, if b is chosen to equal this minimumb_(min), then necessarily a lot of code words contain many transitions.

The number of available code words of length b with i transitions isgiven by $2{\begin{pmatrix}{b - 1} \\i\end{pmatrix}.}$Hence the number of available code words with i transitions increaseswhen the value of b increases. So it is concluded that by choosing kcode words containing the minimum number of transitions as in the codeword selection method above, the resulting number of transitionsτ_(tot)(b), and hence certainly the quantity τ_(tot)(b)/(b−1), decreaseswith increasing b.

This proposition can be set out as follows: the function τ_(tot)(b) is adecreasing function of b for ≧b_(min), that is, if ≧b_(min)≦b<b′, thenτ_(tot)(b)≧τ_(tot)(b)≦τ_(tot)(b′). This observation suggests that${p\left( {k,s} \right)} = {\min\limits_{b \geq b_{\min}}{p\left( {k,s,b} \right)}}$the minimal number of test patterns required in any test set for k netsand satisfying an SSOL constraint s, is realized for a value b that isoften much larger than b_(min).

To indicate the behavior of the bounds mentioned above for varying b,FIG. 9 shows for k=6000 and s=600 both the upper bound${U(b)} = {1 + {\left( {b - 1} \right)\left\lceil \frac{\tau_{tot}(b)}{\left( {b - 1} \right)s} \right\rceil}}$and one of the lower bounds${{L(b)} = {1 + \left\lceil \frac{\tau_{tot}(b)}{s} \right\rceil}},$for b≧b_(min).The best choice for b is close to the first (smallest) value b* of b forwhich the average distance τ_(tot)(b)/(b−1) is at most s. Note that forthis value b*, U(b*)=b*. Below, an estimate is given of the value of b*and hence for corresponding total number of test patterns p(k, s, b) b*,given k and s.Let the number k of code words and the SSOL value s be fixed. As we sawearlier, for each b the value of t is chosen such that$k \approx {2\begin{pmatrix}{b - 1} \\t\end{pmatrix}}$so that by Stirling's approximation:log₂ k≈1+(b−1)/(b−1))where h(x)=−x log₂x−(1−x) log₂(1−x).Also, for the total distance:d _(tot)=τ_(tot) =tkSo d _(tot)≈(b−1)s ift/(b−1)≈s/kCombining these equations gives:P*=b*≈1+(−1+log₂ k)/h(s/k)As it turns out, this estimate for b* is somewhat too small, but alwaysat least about 80% of the true value.

Somewhat surprisingly, it turns out that the optimal value of b, thatis, the value of b that minimizes p(k, s, b), is in fact always equal tothe number b* as defined above, that is, the following result occurs.

Let k and s be positive integers, with k≧2. Define the functionτ_(tot)(b) to be:${\tau_{tot}(b)} = {{\sum\limits_{i = 0}^{t}{ik}_{i}} = {{\sum\limits_{i = 0}^{t - 1}{{i \cdot 2}\begin{pmatrix}{b - 1} \\i\end{pmatrix}}} + {t \cdot k_{t}}}}$Let b_(min)=|log₂k|, and define the number b* to be the smallest integerb≧b_(min) for which τ_(tot)(b)≦(b−1) s. Then the minimum number p(k, s)of test patterns required in any test set for k nets and satisfying anSSOL constraint s satisfies p(k, s)=b*.

As a result of this theorem, to generate a test set for k nets thatsatisfies an SSOL constraint s and contains a minimum number of testpatterns, an embodiment of another aspect of the present invention isillustrated in FIG. 10, and proceeds as follows. Firstly, at step 110,determine the number b* as defined above. Then apply the fixed code wordlength algorithm as described above, with the code words having thefixed length b*. Next, at step 112, choose numbers t and k_(t) accordingto:${k = {{\sum\limits_{i = 0}^{t}k_{i}} = {{\sum\limits_{i = 0}^{t - 1}{2\begin{pmatrix}{b^{*} - 1} \\i\end{pmatrix}}} + k_{t}}}},{{{with}\quad 0} < k_{t} \leq {2\begin{pmatrix}{b^{*} - 1} \\t\end{pmatrix}}}$Next, at step 114, determine the number m=k_(t)* from:$k_{t}^{*} = \left\{ \begin{matrix}{k_{t},} & {{{{if}\quad 0} \leq k_{t} < \begin{pmatrix}{b^{*} - 1} \\t\end{pmatrix}};} \\{{k_{t} - \begin{pmatrix}{b^{*} - 1} \\t\end{pmatrix}},} & {{otherwise}.}\end{matrix} \right.$Next, at step 116, a selection of code words of length b* with at mostt−1 transitions is made, and if m<k_(t) also all words of length b* witht transitions and beginning with a 1.

Finally, at step 118, another m words of length b* with t transitionsand beginning with a 0 (if m<k_(t)) or a 1 (if m≧k_(t). Here, ifmt=q(b*−1)+r, f_(i)=q+1 is chosen for r indices i and f_(i)=q for theremaining b*−1−r indices i. This algorithm then ensures that thedistances d_(j) will be balanced.

This method generates a test pattern set with b* patterns whereconsecutive patterns have a distance of at most s. The method can bereferred to as “ATPG for Variable Code Word Length”.

Experimental results are given below for the new SSOL-constrained ATPGalgorithm and compares those results against results from other methods.True/Complement Tests are used as the basis for the comparison, althoughthe techniques cold be applied to other methods of producing testpattern sets.

In the experimental data, three methods are compared:

1. Conventional Method.

This method generates a True/Complement Test by means of conventionalcounting, followed by complementing. Subsequently, the SSOL constraintis met by conventional insertion of additional test patterns. Thismethod is the basis of many professional (commercially available) tools.

2. Best Method of Marinissen et al.

This method generates a True/Complement Test by means of conventionalcounting, followed by complementing. Subsequently, transition-countbased code word subset selection and test pattern re-ordering areapplied. Remaining SSOL violations are resolved by means of conventionalinsertion of additional test patters. This method is the one thatperformed best from the various methods described in Marinissen et al.

3. ATPG for Variable Code Word Length.

This method generates a “True” test set as described above. This test isguaranteed to be free of SSOL violations and hence does not requireinsertion of additional test patterns. Subsequently, the “Complement”part is generated by adding the complementary test set, which, again, isfree of SSOL violations. At the border between “True” and “Complement”test patterns, usually a few additional test patterns need to beinserted. FIG. 12 shows experimental results for a problem instanceswith kε{5000, 6000, 7000, 8000} nets. For SSOL value s is varyingbetween 5% and 50% of k, FIG. 12 plots the test pattern count p(k, s)for all three methods. FIG. 13 shows the improvements in test patterncount of the previous Marinissen et al method and the new ATPG forVariable Code Word Length relative to the base-line conventional method.

FIGS. 12 and 13 show that, for all SSOL values s, the conventionalmethod yields the highest number of test patterns. For some values of kand s, the best method of Marinissen et al provides substantialimprovement over the conventional method; however, there are also manyvalues of k and s where this method does not yield any improvement atall.

The embodiment of the present invention, the new ATPG for Variable CodeWord Lengths technique, clearly outperforms the other approaches; fork=5000, 6000, 7000, 8000, the average relative improvement over theconventional method is respectively 46%, 46%, 45% and 44%. The new ATPGalgorithm also consistently improves on the conventional method for allvalues of k and s.

An optimal ATPG algorithm has been described that generates, for auser-defined number of nets k, a minimal set of test patterns p(k, s)that respect a user-defined SSOL constraint s. The algorithm is based onthe following observations, which are formalized and proved above.

-   -   The number of test patterns is strongly related to the number of        transitions in the code words. Hence, in order to obtain a valid        test set with a small number of test patterns, we have to select        code word with few transitions.    -   Based on the above observation, an algorithm has been presented        that, for given k, s and b, chooses as code words all of length        b with at most t−1 transitions and subsequently carefully        selects some words of length b with t transitions, such that a        total of exactly k code words is obtained, with balanced Hamming        distance s between consecutive test patterns. The resulting test        set consists of the test patterns thus obtained, plus additional        test patterns inserted to resolve remaining SSOL violations.    -   A second algorithm has been presented that, for given k and s,        finds a value b=b* such that if the above algorithm is invoked        for this b*, it can be guaranteed that no additional test        patterns need to be inserted to meet the SSOL constraint;        moreover, it has been shown that this second algorithm generates        provably minimal test pattern sets.

Using the commonly used True/Complement Test algorithm as an example, wehave presented experimental results for kε{5000, 6000, 7000} and svarying from 5% to 50% of k. The experiments show that the algorithmyields on average 45% reduction in the number of test patterns whencompared to the conventional method.

1. A method of generating digital test sets for testing a number ofwiring interconnects, each test set comprising a matrix of bits, whichmatrix defines a first plurality of test patterns and a second pluralityof code words, wherein the bits of each test pattern are for applicationto respective wiring interconnects in parallel with one another, and thebits of successive test patterns for application to an interconnect forma code word for that interconnect, and wherein each code word has atransition count related to a number of bit value transitions therein,the test set having a total transition count related to the sum of thetransition counts of the code words in the test set, the methodcomprising the steps of generating a test set which has a totaltransition count which is less than a predetermined threshold value, thepredetermined threshold value having a predetermined relationship withthe number of test patterns in the test set.
 2. A method as claimed inclaim 1, wherein the predetermined threshold value has a predeterminedrelationship with a second threshold value.
 3. A method as claimed inclaim 2, wherein the second threshold value is a simultaneous switchingoutput limit for the wiring interconnects.
 4. A method as claimed inclaim 1, wherein the step of generating the test set comprises:generating a first test set which defines a first set of code words; andselecting a subset of the first set of code words, such that the sum ofthe transition counts for the code words in the subset is lower than thepredetermined threshold value.
 5. A method as claimed in claim 4,wherein the step of selecting a subset of code words comprises the stepsof: selecting a first plurality of code words having transition countvalues less than a first value; selecting second plurality of code wordshaving respective transition counts greater than or equal to the firstvalue, such that the sum of the first and second pluralities of codewords selected equals said number of interconnects.
 6. A method asclaimed in claim 1, wherein the number of code words in the test set isequal to said number of wiring interconnects.
 7. A method as claimed inclaim 1, further comprising adding additional test patterns to the testset.
 8. A method as claimed in claim 7, wherein adding additional testpatterns comprises inserting additional test patterns between pairs oftest patterns that have an original transition distance greater than athreshold value, the inserted test patterns causing transition distanceswhich are less than the original transition distance.
 9. A method asclaimed in claim 7, wherein the inserted test patterns cause transitiondistances that are less than or equal to a predetermined thresholdlevel.
 10. A method as claimed in claim 7, wherein adding additionaltest patterns comprises adding the complement of the test set to thetest set to form a final true/complement test set.
 11. A method oftesting a number of wiring interconnects, the method comprising thesteps of: applying a test set, generated in accordance with a method asclaimed in any one of the preceding claims, to a plurality of wiringinterconnects; and analyzing the results of such application.